1. Field of the invention
The present invention relates to the field of semiconductor circuit manufacturing, and more specifically, to a method of forming a contact and a novel integrated circuit structure.
2. Discussion of related art
Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices are interconnected together in order to form functional circuits and components. The devices are interconnected together through the use of multilevel interconnects. A cross-sectional illustration of a typical multilevel interconnect structure 100 is shown in FIG. 1. Interconnect structures normally have a first level of metalization or interconnect layer 105, a second level of metalization 135 and sometimes a third, a fourth, etc., levels of metalization. Interlevel dielectrics 110 (ILDs) such as silicon dioxide (SiO.sub.2) are used to electrically isolate different levels of metalization and silicon substrate 101. The electrical connections between different interconnect levels are made through the use of contact holes 115 formed in ILD 110. Contact holes 115 are filled with a conductive material forming contacts 130 which are used to form electrical connections between interconnect levels and devices formed in substrate 101.
As device dimension decreases, an RC delay associated with the interconnects increase. The RC delay increases the propagation delay associated with the interconnects and thus limits the performance of the circuit. The RC delay is mainly due to the capacitive coupling between metal lines and the resistance of contact material used for the interconnects. The capacitive coupling and the interconnect material are limited by the present methods of forming interconnects.
An example of a technique of forming metal-to-metal contacts through contact holes in a multilevel-interconnect system is shown in FIGS. 2A through 7B. Metal lines 105 are formed on substrate 101, as shown in FIG. 2A. Substrate 101 comprises insulating layer 103 formed over silicon substrate 104. FIG. 2B is a top view showing the location desired of electrical contacts on metal lines 105, as represented by X's 102.
Next, as shown in FIG. 3A, ILD 110 is blanket deposited onto substrate 101 and metal lines 105. Then contact holes 115 are formed through ILD 110, as shown in FIG. 4A. FIG. 4B illustrates locations of contact holes 115. In a process to form contact holes, photoresist 120 is generally deposited over ILD 110 and patterned to define desired locations of electrical contacts. Contact holes 115 are then etched in alignment with patterned photoresist layer 120. After contact holes 115 are formed, photoresist layer 120 is removed.
Next, tungsten (W) 125 is blanket deposited over ILD 110 and into contact holes 115, as shown in FIG. 5A. Tungsten 125 is then polished or etched back so that the top of ILD 110 is exposed, forming filled contacts 130, as shown in FIG. 6A. FIG. 6B shows a top view of contacts 130 after their formation.
To complete the process of forming an interconnect level, a second conductive layer is then deposited over the entire surface. Next, a photoresist layer is deposited over the second conductive layer. The photoresist layer is then patterned. Then, exposed portion of the conductive layer is etched to form metal lines 135. The photoresist is then removed. FIG. 7A shows a cross-sectional view of the partially built multilevel interconnect system after formation of metal lines 135. FIG. 7B shows the locations of metal lines 135. Thereafter, the process described for FIG. 2A through FIG. 7B can be repeated to form additional levels of interconnects.
By using the technique described above, an aspect ratio of 2:1 can be achieved. An aspect ratio is defined as contact width 116 over contact height 117 (see FIG. 4A). Separation of metal lines can increase an aspect ratio. As the aspect ratio increases, capacitive coupling between the metal lines decreases and as the capacitive coupling decreases, the RC delay decreases, resulting in better circuit performance. Hence, an aspect ratio that is greater than 2:1 is desirable. Since the contacts are formed by filling contact holes, as the aspect ratio of the contact holes increases, the probability of void formation also increases. Therefore, an aspect ratio that is greater than 2:1 cannot be achieved by using the current technique.
An additional problem with the current technique is that only tungsten can be used to fill contact holes. Tungsten 125 is used in a multilevel-interconnect system because it can be deposited by chemical vapor deposition (CVD). CVD allows a material to be deposited conformally which allows a complete fill of contact holes 115 with an aspect ratio of 2:1. A material with a lower resistance than that of tungsten such as aluminum, copper, gold, silver, and their alloys, is more desirable as a contact material in filling contact holes 115. However, such low resistance materials cannot be used because they can only be reliably deposited by sputtering, rather than by CVD. Sputtering processes typically do not allow a material to be deposited conformally and as a consequence, only contact holes with aspect ratios of less than 2:1 can be filled reliably.
As pointed out above, one method to minimize the RC delay is to decrease the capacitive coupling between metal layers by increasing the distance between the metal layers. However, with the present method in forming contacts, the aspect ratio is limited to 2:1 due to the problem of void formation associated with filling the contact holes. A second way to minimize the RC delay is to use a low resistance contact material. However, low resistance materials such as aluminum, copper, silver, gold and their alloys can only be deposited by sputtering, thus cannot be used to fill contact holes with an aspect ratio of greater than 2:1.
Thus, what is desired is a method of forming a high aspect ratio contact, utilizing low resistance materials.